Image showing completely notch free features
by Dean Stephens, Senior Applications Engineer, OIPT
For the fabrication of sub-micron silicon features for MEMS applications it is necessary to form openings with vertical sidewall profiles, and to maintain the critical dimension defined by the previous lithographic steps.
Plasma etching of silicon at cryogenic temperatures - typically in the range -150ºC to -50ºC produces such vertical sidewall profiles.
In cryogenic etching, anisotropy is facilitated by sidewall passivation provided by SiOxFy condensation at these low temperatures. This method has the advantage that it does not rely on polymer formation to provide sidewall passivation and hence does not affect the critical dimension. The anisotropy of the etch, being controlled by temperature and oxygen content, allows control over the sidewall angle.
A small amount of mask undercut is often however, an unavoidable feature of cryogenic etching, reducing the silicon etch depth that can be attained during the etching of sub-micron features due to mask lift-off. OIPT has previously patented a technique “Oxy-thermal Burst” that produces enhanced passivation during the initiation of the silicon etching, practically eliminating undercut and allowing deep silicon etching of sub-micron features.
This technique primarily utilises two steps, and controls the undercut by temporarily altering temperature and oxygen content, allowing greater control over initial sidewall slope / mask undercut. This technique is applicable to any form of Cryo-etching, i.e. in both RIE or ICP tools, and etching any suitable material.
OIPT has now evolved the concept further and developed a method that continuously varies the sidewall passivation over the course of the initial portion of the etch, which has been shown to completely eliminate the problem of mask undercut.
Work was carried out on a System100 ICP180 fitted with a cryogenic electrode, using variations of the two step “oxy-thermal burst” process, tuning process parameters such as pressure, RF power and gas flows. It was found that this approach could merely reduce the amount of notching, or undercut, seen but could not fully eliminate it.
A strategy was then used that included performing a physical sputter process on the wafer, pre-etch, in order to expose some trench sidewall for passivation to form on the sidewall from the very beginning of the “etch proper”. This was found to reduce the notching effect, creating a reproduction of the mask facet angle beneath the mask – effectively reversing the angle of the notch.
At this point, it was noted that during two step processing, the depth of the undercut would correspond with the etch depth of the first step when performed alone.
It was then decided that, perhaps, the best solution would be to ramp the O2:SF6 ratio, in the initial portion of the etch – mimicking the two step process’ initial high ratio of O2:SF6 , but, using parameter ramping, to gradually reduce it in stages until the main etch step began. This gave superior passivation coverage at the top of the feature to better resist breakdown, during the main etch stage, of the “thinned” passivation at the top of the trench.
The initial conditions of this etch virtually eliminated the notch, proving very encouraging. Work then concentrated around establishing the optimum conditions for the O2:SF6 ramp, to give a notch free etch. Conditions were found which accomplished this, repeatedly giving no notch at the top of the etch trench.
The exact curve of this “passivation ramp” will be different for each individual mask – it is clear from work already carried out that the value is simply tuned and that individual masks are easily catered for.
These process modifications have shown that smooth sidewall cryogenic etching can, indeed, be performed without the inherent problem of mask undercut, thus no longer limiting the usefulness of this technique in sub-micron feature etching.
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